![]() ![]() Where r is a 8-bit general purpose register and n is a one-byte operand. Now, let’s delve into the LD instructions that use immediate addressing. In summary, for the 64 possible binary codes for the template 0b01 r r’, we have 63 8-bit register move instructions and one outlander HALT instruction. Likewise, we also have seven store counterparts: 76 543 210 01 110 r -> LD (HL), rīut, what about the binary code 0b01110110? Is it a valid load instruction? As it wouldn’t make much sense to waste machine cycles only to load a memory location with its own content, this binary code was set to correspond to the HALT instruction. Then we have 7 more load instructions of the type: 76 543 210 01 r 110 -> LD r, (HL) Remember this scheme was borrowed from the 8080 CPU. You could think of (HL) as a special type of register anyway. ![]() Rather, it stands for the indirect addressing expressed by (HL). Well, it happens that 0b110 is a valid value indeed, but it doesn’t correspond to a CPU internal register. ![]() But, what about the 15 binary combinations left? (did you noticed the missing value 0b110 for the register field?). So, we have 49 valid 8-bit register-only load instructions. Thus, these are valid op-codes: 01 010 111 -> LD D, A Notice that this instruction type has two register fields (register addressing mode), and any one can have one of the following values: Bits Where r and r’ are 8-bit registers within the currently active register set. The generic form for instructions that move 8-bit data between registers is: LD r, r' Which means operand1 receives the value indicated by operand2, i.e., operand1 ← operand2. The Zilog engineers kept binary code compatibility with the 8080, while expanding the design with new and extended instructions.Ī generic load instruction takes the following form: LD operand1, operand2 It is important to say upfront that most of Z80 instruction’s design was taken from the Intel’s 8080 CPU. Let’s examine how the load instructions are structured in the Z80. ![]()
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